A voltage-mode R-2R digital-to-analog converter (DAC) includes resistor legs that are switched between two reference voltages (Vref and the ground Vgnd) using a single-pole, double-throw switch. FIG. 1 illustrates a segmented voltage-mode R-2R DAC 100 that converts a digital code input into an analog voltage output (Vout). The segmented voltage-mode R2R DAC 100 may include a resistor ladder that further includes a number of legs. Each leg may include a resistor (2R) and a switch 106.1-106.6 so that the resistor (2R) is switchably connected to either a first position that connects to the ground (Vgnd) or a second position that connects to a reference voltage potential (Vref). The switches 106.1-106.6 are MOS switch pairs that are discussed in detail along with FIG. 2. Each leg of the resistor ladder (including a corresponding switch pair) is controlled by a bit of the digital code according to an order of a least significant bit (LSB) at the left side to a most significant bit (MSB) at the right side. If the bit value equals zero, the switch is switched to the first position so that the corresponding leg is connected to Vgnd; if the bit value equals one, the switch is switched to the second position so that the corresponding leg is connected to Vref. Thus, the digital code may be converted into an analog voltage output (Vout) through voltage attenuation over the resistor ladder.
The segmented voltage-mode R-2R DAC 100 may be divided into two portions. A first portion on the left side of the dashed line is an R-2R DAC 102, and a second portion on the right side of the dashed line is a segmental DAC 104. The R-2R DAC 102 may include digital bits of lower significance, while the segmented DAC may include bits of higher significance. Together, the R-2R DAC 102 and the segmental DAC 104 form the segmented voltage-mode R-2R DAC 100.
FIG. 2 illustrates a detailed circuit schematic for the MOS switches 106.1-106.6. Referring to FIG. 2, a switch 200 (that can be any one of the MOS switches 106.1-106.6) receives a digital bit B(N) and outputs a voltage of Vgnd or Vref to the resistor (2R) in a leg of the segmented voltage-mode R-2R DAC. The switch 200 includes drivers 202, 204, and a p-channel MOSFET (PMOS) 206, and an n-channel MOSFET (NMOS) 208. The drivers 202, 204 respectively receive the digital bit B(N), while the outputs of drivers 202, 204 are coupled to the gates of the PMOS 206 and NMOS 208, respectively. Based on the digital input, the output of driver 202 may be driven to either a reference voltage Vgp or a positive supply voltage Vdd, and the output of driver 204 may be driven to either a reference voltage Vgn or a negative supply voltage Vss. In operation, the PMOS 206 and the NMOS 208 form a complementary MOS switch pair so that, at any moment, if the gate voltage of the PMOS 206 is at Vgp, the gate voltage of the NMOS 208 is at Vss; or alternatively, if the gate voltage of the PMOS 206 is at Vdd, the gate voltage of the NMOS 208 is at Vgn. Therefore, at any moment, only one of PMOS 206 and NMOS 208 is on.
An ideal switch, when it is ON (or engaged), has zero resistance. However, in practice, when PMOS 206 or NMOS 208 is ON, each of the MOS switches has an ON resistance. Further, the ON resistance for PMOS 206 is commonly different from the ON resistance for NMOS 208. This unequal ON resistances between PMOS 206 and NMOS 208 cause inaccuracy in the DAC output. U.S. Pat. No. 5,075,677 (the '677 patent) (assigned to the assignee of the present application) describes a Vgn generator circuit that supplies adjustable Vgn (or similarly, adjustable Vgp) to driver 204 (or similarly, driver 202) so that the apparent ON resistances for the PMOS and NMOS switches are substantially same.
FIG. 3 illustrates a Vgn generator as described in the '677 patent. Referring to FIG. 3, the Vgn generator 300 includes an op-amp 302, a PMOS 304, an NMOS 306, and resistors 308-314. Resistors 308, 310 are selected to have a same first resistance (R1) within a precision range, and resistors 312, 314 are selected to have a same second resistance (R2) within a precision range. Since the resistors 312, 314 are selected to have a same second resistance, the voltage at node 318 is Vref/2 which is supplied to the inverted input of the op-amp 302. By operation of the op-amp 302, the voltage at the non-inverted input of the op-amp 302 follows the inverted input and also equals to Vref/2. Further, since resistors 308, 310 also have the same resistance, the voltage drops over resistors 308, 310 are also the same and thereby Vds for PMOS 304 equals Vds for NMOS 306. The Vds balance between PMOS 304 and NMOS 306 is achieved by adjusting Vgn as the gate of the NMOS 306. The adjustable Vgn is applied to the gate of the NMOS switch 208. In this way, the '677 patent chooses Vgn for NMOS switch which results in equalizing the ON resistances between the NMOS switch 208 and the PMOS switch 206. While FIG. 3 illustrates a Vgn generator, a person of ordinary skill in the art would understand that a Vgp generator may be similarly constructed with the output being coupled to the gate of PMOS 304 and the gate of NMOS 306 being coupled to Vref. Therefore, the following embodiments are discussed in terms of the Vgn generator for convenience.
To reduce sensitivity to the input offset (Vos) of op-amp 302 and to reduce sensitivity to resistor mismatches, current art uses a moderately large Vds for the PMOS 304 and NMOS 306 in the Vgn generator so that they are much larger than Vds for PMOS 206 and NMOS 208, namely, Vds [Vgn]>>Vds [DAC]. However, as shown in the following, this causes non-linearity in the resistor legs in the DAC, which is undesirable, especially for bits of higher significance such as MSB.